1. Field of the Invention
The present invention relates generally to the field of integrated circuits, and more particularly, integrated circuits having switching capabilities.
2. Description of the Related Art
A programmable logic device or PLD is a programmable integrated circuit that allows the user of the circuit, using software control, to customize the logic functions the circuit will perform. The logic functions previously performed by small, medium, and large-scale integration integrated circuits can instead be performed by programmable logic devices. When an integrated circuit manufacturer supplies a typical programmable logic device, it is not yet capable of performing any specific function. The user, in conjunction with software supplied by the manufacturer or created by the user or an affiliated source, can program the PLD to perform the specific function or functions required by the user""s application. The PLD then can function in a larger system designed by the user just as though dedicated logic chips were employed. For the purpose of this description, it is to be understood that a programmable logic device refers to once programmable as well as re-programmable devices.
Programmable logic encompasses all digital logic circuits configured by the end user, including field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs). FIG. 1A is an illustration of a CPLD 100 known as embedded array programmable logic. The general architecture of the embedded array programmable logic device will be generally familiar to those knowledgeable of the FLEXIOK(trademark) logic family of devices manufactured by the Altera Corporation of San Jose, Calif. Such an architecture is described in U.S. Pat. No. 5,550,782 and Altera Data Book 1998, which are incorporated herein by reference. Although only a few logic array blocks or memory blocks are illustrated, it should be appreciated that any number may be provided in order to meet the needs of a particular system.
Using the described embedded array type architecture, logic functions may be formed from each logic array block, or LAB, and various memory/logic functions may be formed from each embedded array block, or EAB. Each EAB and LAB may be programmably coupled to a plurality of vertical and horizontal conductors by appropriately situated associated programmable connectors such that an array capable of performing complex logic as well as complex logic/memory operations is formed. Each EAB includes an array of memory cells capable of operation as either a random access memory, static random access memory, dynamic access memory, or other configurations suitable for a desired application.
As an example, LAB 102 may be electrically coupled to a horizontal conductors 174 and 176 by programmable connectors 180 and 182, respectively and vertical conductors 190 and 194 by programmable connectors 184 and 186, respectively. In a similar fashion each of the array of EABs may be electrically coupled to at least one of each of the plurality of vertical and horizontal conductors. By way of example, EAB 104 may be electrically coupled to vertical conductors 190 and 191 by way of programmable connectors 195 and 197, respectively, and horizontal conductors 174 and 176 by way of programmable connectors 193 and 199, respectively. In this way, an embedded array programmable logic device capable of implementing complex logic and combined logic/memory functions is formed.
Cross-bar switches are commonly used in networking applications, such as switched LAN and ATM. Cross-bar switching schemes are also commonly used in telecommunications, networking, digital signal processing and multiprocessing systems. The basic building block in these switching schemes is an N inputxe2x88x92N output (Nxc3x97N) cross-bar switch 150 as illustrated in FIG. 1B. The Nxc3x97N cross-bar switch 150 is capable of passing data between any one of a first plurality of the N bi-directional ports 152 to any one of a second plurality of N bi-directional ports 154.
Cross-bar switches perform many different tasks in addition to signal routing. For example, in some switching architectures, the destination address is embedded in the packetized data that is being rerouted. These switches perform address stripping and translation, assign routing channels, and may even provide some buffering for data packets.
Because cross-bar switches contain functionality in addition to pure signal routing, they are usually implemented as ASICs (Application Specific Integrated Circuits). An ATM (Asynchronous Transfer Mode) switch used extensively in networks such as LANs, WANs, and the Internet is but one example of a cross bar switch containing functionality. In the case of the ATM switch cited, such functionality may include Quality of Service (QoS) and traffic control functions in addition to the more conventional signal routing associated with a cross bar switch.
Unfortunately, cross-bar switches implemented as ASICs have several disadvantages. One such disadvantage is the time-to-market risks associated with the relatively long cycle time necessary for the implementation of a new ASIC design. An additional disadvantage with the use of ASICs for cross bar switches is the fact that ASIC based cross-bar switches cannot be used for re-configurable applications since ASICs are xe2x80x9chardwiredxe2x80x9d and must be redesigned for any new application.
In view of the foregoing, it is advantageous and therefore desirable to have available a programmable logic device which is capable of being user selected to perform complex logic functions in concert with or independent of cross-bar switch based signal routing and processing functions.
The invention relates to an integrated circuit that is operable in a plurality of switching modes is disclosed. The integrated circuit includes a plurality of direct connectors and a programmable switch unit operable in a plurality of switching modes. The programmable switch unit has a plurality of bi-directional I/O ports selectively connected by way of programmable switch unit internal connectors. The integrated circuit also includes a programmable function unit directly connected to the programmable switch unit by way of the direct connectors. The programmable function unit is programmably configured to operate as required by a selected one of the plurality of switching modes. As required by the selected one of the plurality of switching modes, the programmable function unit directs the programmable switch unit to form internal connections using the programmable switch unit internal connectors such that that programmable switch unit passes signals between selected portions of the plurality of bi-directional I/O ports.
In another aspect of the invention, a programmable logic device operable as a programmable switching device is disclosed. The programmable logic device includes a plurality of interconnection lines and a plurality of bi-directional input/output (I/O) ports that can be connected to external circuitry. The programmable logic device also includes a programmable function block that can be programmably connected to the plurality of bi-directional I/O ports via the plurality of interconnection lines. The programmable logic device also includes a programmable switch unit having a first plurality of I/O lines and a second plurality of I/O lines such that a selected portion of the first plurality of I/O lines can be directed by the programmable function block as needed to connect with a selected portion of the second plurality of I/O lines. In this way, that signals can pass between the selected portions of the first and the second plurality of I/O lines as required by programmable switching device.
The advantages of the invention are numerous. One advantage of the-invention is the increased routability that results due to the more efficient use of a limited number of memory resources. By using less die area for the placement of memory resources, the available die area for the inclusion of additional routing and/or memory and logic elements is increased. Another advantage is that the risk of fitting a logic function with unacceptable performance problems caused by circuitous routing is substantially reduced since the logic blocks and the memory blocks, for example, are located in closer physical proximity than would be available in conventional CPLD architectures. Consequently, the increased flexibility enables the CPLD to fit more complex logic functions more often than possible with conventional CPLD architectures.